Resolved Logic Vectors
In real hardware, there are times when we need to model tristate bus. So that multiple agents can drive same bus. Like PCI bus or Microprocessor 8085 address and data bus.

Array Of Ports/Signals

SystemC allows to declare Array of ports and signals. This is very useful when we need to create array of similar ports and signals. 

Introduction
In this chapter we shall see ports and signal types in details.

Accessing Ports/Signals

sc_fifo

sc_fifo is a predefined primitive channel intended to model the behavior of a fifo, that is, a first-in first-out buffer. A fifo is an object of class sc_fifo. Each fifo has a number of slots for storing values. 

sc_semaphore
sc_semaphore is a predefined primitive channel intended to model the behavior of a software semaphore as used to provide limited concurrent access to a shared resource. A semaphore has an integer value, the semaphore value, which is set to the permitted number of concurrent accesses when the semaphore is constructed.

sc_mutex

sc_mutex is a predefined primitive channel intended to model the behavior of a mutual exclusion lock as used to control access to a resource shared by concurrent processes.

 

Introduction

SystemC provides Channels for communication between two modules. This Channels make complex communication easy. SystemC has two types of channels.

 

SystemVerilog DPI Interface

SystemVerilog DPI is much more easy to interface with external C like languages. We can still use the exisiting TF and ACC routines. Below is same example shown with VPI.

VPI Interface File

  1 #include 

SystemC Counter Exports

  1 #ifndef COUNTER_TB_EXPORTS_H

  2 #define COUNTER_TB_EXPORTS_H

Verilog DUT

  1 `timescale 1ns / 1ns

  2 // Verilog DUT

Compile Commands

# Point to your systemC home

 SYSTEMC_HOME = /appl/systemc

SystemC Ports

  1 #ifndef MEMORY_TB_PORTS_H

  2 #define MEMORY_TB_PORTS_H

SystemC TxGen Header File

  1 #ifndef MEMORY_TXGEN_H

  2 #define MEMORY_TXGEN_H

Verilog DUT

  1 // Simple Verilog Memory Model

  2 module memory(