With innovations in technologies and methodology, the benefits of formal functional verification apply in many more areas. If we understand the characteristics of areas with high formal applicability, we can identify not only which blocks are good candidates, but also what portions or functionalities of the blocks will give the greatest return on the time and effort invested. Today, formal verification can be more valuable applied partially within blocks by choosing the functions that have the highest return.

Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two years. The chip makers want to pack as many functions as possible in their SoCs and provide as many feature additions to gain market share. The additional features increase the complexity and effort for verification.

I. Introduction

Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction, multiplication, division, parity calculation. Most of the time, designing these circuits is the same as designing muxers, encoders and decoders.

 

 

1. Introduction to Structs

The basic organization of an e program is a tree of structs. A struct is a compound type that contains data fields, procedural methods, and other members.

It is the e equivalent of a class in other object-oriented languages. 

1.     

Conditional Flow Control: Conditional flow like in any other programming language is used for controlling execution a block of code, when a condition is true.

2.     Content

-      Conditional Flow Control Part-I

1.    Digital Logic Families

Logic families can be classified broadly according to the technologies they are built with. In earlier days we had vast number of these technologies, as you can see in the list below.

DL : Diode Logic.

   1.    Introduction to Coverage

   Typically in verification flow, we do code coverage, but doing code coverage shows only if all the lines of the DUT is executed, if all the possible cases of a expression are covered. 

1. Temporal Expression Recognition

Temporal Expression Recognition (TER) is the process of locating phrases that denote temporal information. Temporal expressions may be an expressed point in time, a duration or a frequency. 

1. About this document

This document has three target audiences. Those who are not at all familiar with Specman should find in the first chapter a brief objective account of its main working principles and a discussion of its pros and cons. 

ABSTRACT

An improved technique for fifo design is to perform asynchronous comparisons between the fifo write and read pointers that are generated in

1. Overview

If the designer creates the product, the simulator is the person who ensures that the product has to meet the best quality when it reaches the customer. 

1. Overview

If the designer creates the product, the simulator is the person who ensures that the product has to meet the best quality when it reaches the customer. 

UART Scoreboard

  1 <'

  2 struct uart_sb {

Device Under Test

   1 //-----------------------------------------------------

   2 // Design Name : uart