Before We Start

Before we jump into the details of SystemC language, lets looks at what SystemC offers for hardware modelling in brief.

Introduction
The SystemC Class Library has been developed to support system level design. It runs on both PC and UNIX platforms, and is freely downloadable from the web.

Basics of C++.

It is probably best to look at concrete examples of object oriented programming in C++ before going into further theory or concepts. We'll consider two kinds of examples.

Introduction
C++ was developed by Bjarne Stroustrup of AT&T Bell Laboratories in the early 1980's, and is based on the C language. The name is a pun - "++" is a syntactic construct used in C (to increment a variable), and C++ is intended as an incremental improvement of C.

Module Instanciating
Instanciating modules in SystemC is same as in Verilog, same rules are followed. SystemC like Verilog allows two ways of connecting ports.

Module Ports
Module Ports pass data to and from the processes of a module to the external world as in Verilog and VHDL. You declare a port direction as in, out, or inout. You also declare the data type of the port as any C++ data type,

Introduction
Modules are the basic building block within SystemC to partition a design. Modules allow designers to break complex systems into smaller more manageable pieces. 

next_trigger()
next_trigger() is used with process methods, one's which are not threads. The function next_trigger does not suspend the method process instance; a method process cannot be suspended,

wait()
wait() suspends the thread or clocked thread process instance from which it is called for the very next occasion on which that process instance is resumed, and for that occasion only.

sc_event

sc_event is same as event in Verilog. It is used for process synchronization. A process instance may be triggered or resumed on the occurrence of an event, that is, when the event is notified.

sc_time_stamp ()

The function sc_time_stamp return's the current simulation time. During elaboration and initialization the function will return a value of zero.

sc_start

sc_start() is a key method in SystemC. This method starts the simulation phase, which consists of initialization and execution. sc_start() methods performs operations listed below.

Introduction
Difference between a HDL and other programming language is notion of time and concurrancy. In this chapter we will see the time data type in detail.

Clocks

Clocks are special objects in SystemC. They are used for generating clocks, that are used for synchronizing the events in SystemC models link in any other HDL.

Signal Binding

Each port should be bound to a single signal. When reading a ports, the variable assigned to the port must have the same type as the port type.