ntroduction
When SystemC is purely used for modelling purpose, SystemC can be run in standalone mode. But when SystemC Verification Extension is used for Verifying HDL DUT,
like one written in Verilog, then we need to interface SystemC to Verilog/VHDL simulator.
Verilog Simulator Interface
Interfacing with Verilog simulator is very straight forward. This is due to the fact that Verilog language defines Programming Language Interface (PLI) for interfacing with C or C++ code. Which is external to Verilog Simulator.
I am going to show how to interface with PLI 1.0 and PLI 2.0 (VPI). Followed by DPI which is latest SystemVerilog way of interfacing.
PLI 1.0 Interface
For the SystemC to work with Verilog PLI following sequence of operations need to be performed.
- Callback :Add callback on all the output signals of HDL, clock and reset in such a way that, when ever they change. PLI code gets control.
- Sample : Sample all the inputs to SystemC or outputs of HDL.
- sc_start(time) : sc_start method of systemC with parameter time. Where time is difference between last call time and current time.
- Drive : Drive all the outputs of SystemC or inputs to HDL
| Other then this, we need to perform few other tasks listed below. |
- Initilize the SystemC Model, when PLI task is executed for first time.
- Type conversion between SystemC and PLI
- Terminate SystemC model, Like closing VCD file, when $finish is encountered in HDL.
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