Before We Start

Before we jump into the details of SystemC language, lets looks at what SystemC offers for hardware modelling in brief.

• Modules and Hierarchy
• Hardware Data Types
• Methods and Threads
• Events, Sensitivity
• Interfaces and Channels

Modules and Hierarchy
Modules are building blocks of SystemC designs, they are like modules in Verilog, class in C++. Modules can instanciated in another Module, Each of the lower level modules instance can be refered through the complete hierarchy. This is same as in Verilog or C++.

Hardware Data Types
To model the hardware, SystemC provides SystemC datatypes which are very close to Verilog Data types.Some of this data types are sc_logic and sc_lv. Hardware data types for mathematical calculations like sc_fixed and sc_int allow modeling of complex calculations like DSP functions and evaluate the performance when implemented in custom hardware or in processors without full floating-point capability. There are other complex datatypes, we will see them in detail in data types chapter.
Since SystemC is based on C++, it supports all the C++ data types. In general it is good idea to use C++ data types where SystemC data types is not required. SystemC data types consume more memory and tend to slow down simulation.

Methods and Threads

Events, Sensitivity
Events and Sensitivity give SystemC power to emulate hardware (concurrency). Events are implemented by the SystemC sc_event class. Events are caused or triggered through the sc_event member function.
SystemC has two types of sensitivity: static and dynamic. Static sensitivity is implemented by applying the SystemC sensitive command to an SC_METHOD, SC_THREAD, or SC_CTHREAD at elaboration time (within the constructor). Dynamic sensitivity lets a simulation process change its sensitivity on the fly. The SC_METHOD implements dynamic sensitivity with a next_trigger command. The SC_THREAD implements dynamic sensitivity with a next command.

Interfaces and Channels
In real hardware pins (ports) are used for communicating with external world. In SystemC, modules are interconnected using either primitive channels or hierarchical channels. Both types of channels connect to modules via ports.

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