Module Ports
Module Ports pass data to and from the processes of a module to the external world as in Verilog and VHDL. You declare a port direction as in, out, or inout. You also declare the data type of the port as any C++ data type,

SystemC data type, or user defined type.
Types of Ports

• in : Input Ports
• out : Output Ports
• inout : Bi-direction Ports
  Port modes sc_in, sc_out, and sc_inout are predefined by the SystemC class library.
  Syntax :

• port_direction : One of the sc_in,sc_out,sc_inout
• type : Data type
• variable : Valid variable name

Example Module Ports

  1 #include "systemc.h"

  2

  3 SC_MODULE (first_counter) {

  4   sc_in_clk     clock ;      // Clock input of the design

  5   sc_in<bool>   reset ;      // active high, synchronous Reset input

  6   sc_in<bool>   enable;      // Active high enable signal for counter

  7   sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter

  8

  9   // Rest of body

 10 }
Module Signals

Ports are used for communicating outside the module. For communicating within a SystemC module we use signals. Signals are like wires in Verilog. Signals can be of any legal data types.
Signal are also used for connecting two modules ports in parent module. Lets say we have two child modules A and B, this two modules are used in parent module C, then wires are used for connecting ports of module A and B with each other.
Syntax :
 sc_signal type variable;

Here :

• sc_signal : Reserved word
• type : Data type
• variable : Valid variable name

Example Module Signal

 1 #include "systemc.h"

 2

 3 SC_MODULE (counter) {

 4   sc_signal <bool>        reset ;     

 5   sc_signal <bool>        enable;     

 6   sc_signal <sc_uint<4> > counter_out;

 7

 8   // Rest of body

 9 }

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