Introduction
The SystemC Class Library has been developed to support system level design. It runs on both PC and UNIX platforms, and is freely downloadable from the web.

The class library is being released in stages. The first stage, release 1.0 (presently at version 1.0.2) provides all the necessary modelling facilities to describe systems similar to those which can be described using a hardware description language, such as VHDL. Version 1.0 provides a simulation kernel, data types appropriate for fixed point arithmetic, communication channels which behave like pieces of wire (signals), and modules to break down a design into smaller parts.
In Release 2.0 (presently at version 2.0.1), the class library has been extensively re-written to provide an upgrade path into true system level design. Features that were built-in to version 1.0, such as signals, are now built upon an underlying structure of channels, interfaces, and ports. Events have been provided as a primitive means of triggering behaviour, together with a set of primitive channels such as FIFO and mutex. Version 2.0 allows much more powerful modelling to be achieved by modelling at the level of transactions.
In future, Version 3.0 of the class library will be extended to cover modelling of operating systems, to support the development of models of embedded software.
It is also possible to provide additional libraries to support a particular design methodology. Examples of this are the Master-Slave Communication Library, and the SystemC Verification Library (SCV).

The SystemC Class Library has been developed by a group of companies forming the Open SystemC Initiative (OSCI). For more information, and to download the freely available source code

  1 // D-FF Code

  2 #include "systemc.h"

  3

  4 SC_MODULE(d_ff) {

  5   sc_in<bool> din;

  6   sc_in<bool> clock;

  7   sc_out<bool> dout;

  8  

  9   void doit() {

 10     dout = din;

 11   };

 12  

 13   SC_CTOR(d_ff) {

 14     SC_METHOD(doit);

 15     sensitive_pos << clock;

 16   }

 17 };

One can describe a simple Flip flop as that in above figure as well as one can describe a complicated designs. SystemC is one of the languages available in the industry for modelling the Hardware. SystemC allows us to design a Digital design at very high level. SystemC allows hardware designers to express their designs with behavioral constructs, deterring the details of implementation to a later stage of design in the final design. With addition of SystemC Verification, same lanugage can be used for design and also for verification.

SystemC is based on C++, so you can use the standard C++ programming language development tools available to create, simulate, debug and ex­plore various architectural and algorithmic descriptions of your design. Also since it is C++, a SystemC model can be compiled on a multitude of C++ compilers on several platforms. Figure 1-1 shows you how to use a SystemC model in a standard C++ development environment. You can use exactly the same set of tools to write and debug SystemC models (af­ter all, it is C++). The SystemC model is often called the executable spec­ification', this is because you can compile and execute the SystemC model to understand the behavior of the system

You can effectively use SystemC to describe a cycle-accurate model of your design. SystemC also provides a methodology for describing.

• system level design
• software algorithms
• hardware architecture

SystemC provides a single language to define hardware and software components, it provides a single language to facilitate seamless hardware software cosimulation, and provides a single language to facilitate step-by-step refinement of a system design down to the register transfer level for synthesis.

Many engineers who want to learn SystemC, most often ask this question, how much time it will take to learn SystemC?, Well my answer to them is "It may not take more then one week, if you happen to know at least one programming language and a bit about OOPS".

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