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SystemC Modules Part III

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Module Instanciating
Instanciating modules in SystemC is same as in Verilog, same rules are followed. SystemC like Verilog allows two ways of connecting ports.

  • By Name
  • By Position

By Position
Here order should match correctly. Normally it not a good idea to connect ports by position. Could cause problem in debug (For example : locate the port which is causing compiler compile error), when any new port is added or deleted. Below is example of connecting ports by position.

  1 #include "systemc.h"

  2 #include "first_counter.cpp"

  3

  4 int sc_main (int argc, char* argv[]) {

  5   sc_signal<bool>   clock;

  6   sc_signal<bool>   reset;

  7   sc_signal<bool>   enable;

  8   sc_signal<sc_uint<4> > counter_out;

  9   int i = 0;

 10   // Connect the DUT

 11   first_counter counter("COUNTER");

 12     // Here ports are connected by position

 13     counter(clock,reset,enable,counter_out);

 14

 15   // Rest of the body of the testbench

 16

 17   return 0;// Terminate simulation

 18  }
By Named

Here the name should match with the leaf module, the order is not important. Below is example of connecting ports by name.

  1 #include "systemc.h"

  2 #include "first_counter.cpp"

  3

  4 int sc_main (int argc, char* argv[]) {

  5   sc_signal<bool>   clock;

  6   sc_signal<bool>   reset;

  7   sc_signal<bool>   enable;

  8   sc_signal<sc_uint<4> > counter_out;

  9   int i = 0;

 10   // Connect the DUT

 11   first_counter counter("COUNTER");

 12     // Here ports are connected by name

 13     counter.enable(enable);

 14     counter.reset(reset);

 15     counter.clock(clock);

 16     counter.counter_out(counter_out);

 17

 18   // Rest of the body

 19

 20   return 0;// Terminate simulation

 21  }

Internal Variables

SystemC allows usage of local variable like Verilog or any other programming language. This local variables can be of any legal C++ or SystemC or user defined types. Refer to data types chapter for valid SystemC data types
Example Internal Variables

  1 #include "systemc.h"

  2

  3 SC_MODULE (local_variable) {

  4   sc_in_clk     clock ;      // Clock input of the design

  5   sc_in<bool>   reset ;      // active high, synchronous Reset input

  6   sc_in<bool>   enable;      // Active high enable signal for counter

  7   sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter

  8

  9   //------------Local Variables Here---------------------

 10   sc_uint<4> count;

 11

 12   //------------Code Starts Here-------------------------

 13   // Below function implements actual counter logic

 14   void incr_count () {

 15     // Body of the function

 16   } // End of function incr_count

 17

 18   // Constructor for the counter

 19   SC_CTOR(local_variable) {

 20     cout<<"Executing new"<<endl;

 21     SC_METHOD(incr_count);

 22     sensitive << reset;

 23     sensitive << clock.pos();

 24   } // End of Constructor

 25

 26 }; // End of Module counter

Processes

Actual functionality of SystemC module is implemented in Processes. This is same as always block of Verilog. Process can be either made level sensitive to model combonational logic or can be made edge sensitive logic, to module sequential logic.
Process can be made to run for ever, by forking them like Verilog. We call this as threads in SystemC. Or run when ever a event occures (Example : posedge of clock).
Note :
 Sensitive list signals which trigger a process/thread should ports and can not be a signal or local variable
Example : Processes

  1 #include "systemc.h"

  2

  3 SC_MODULE(dff) {

  4   sc_in  <bool> din; // Data input of FF

  5   sc_in  <bool> clk; // Clock input of FF

  6   sc_out <bool> out; // Q output of FF

  7  

  8   void implement();  // Process that implements DFF

  9  

 10   SC_CTOR(dff) {

 11     SC_METHOD(implement);

 12     sensitive_pos << clk; // Call implements() at every pos edge of clk

 13   }

 14 };
Constructor

The module constructor creates and initializes an instance of a module. The constructor creates the internal data structures that are used for the module and initializes these data structures to known values. The module constructors in SystemC are implemented such that the Modules and Hierarchy instance name of the module is passed to the constructor at instantiation (creation) time. This helps identify the module when errors occur or when reporting information from the module. This is only difference between a constructor of C++ and SystemC.


Example Constructor

  1 #include "systemc.h"

  2

  3 SC_MODULE(dff) {

  4   sc_in  <bool> din; // Data input of FF

  5   sc_in  <bool> clk; // Clock input of FF

  6   sc_out <bool> dout;// Q output of FF

  7  

  8   void implement() {  // Process that implements DFF

  9     dout = din;

 10   }

 11  

 12   SC_CTOR(dff) {

 13     SC_METHOD(implement); // Contains a process named implement

 14     sensitive_pos << clk; // Execute implements() at every posedge of clk

 15   }

 16 };

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Lần cập nhật cuối ( Chủ nhật, 12 Tháng 6 2022 21:34 )  
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