Being one of the most complex supply chains in the world, the semiconductor supply chain is worth around $0.5 trillion and is often very difficult to understand and manipulate. But before we dive deeper, we need to know what a supply chain is and how it impacts the world around us.

The streaming operator uses the terminology pack when you take multiple variables and stream them into a single variable. And conversely, unpack is when you stream a single variable into multiple variables.

Dynamic Array: Usage of dynamic array when user to allocate its size for storage during run time.

Dynamic array store a contiguous collection of data.

The array indexing should be always integer type.

UVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology in terms of architecting testbenches and test cases, and also comes with a library of classes that helps in building efficient constrained random testbenches easily.

Inheritance in SystemVerilog is the most commonly used principles of Object Oriented Programming (OOP) that facilitates reuse. It’s called Inheritance because it creates new classes taking all the existing Properties and Methods from the Base Class or Super Class.

Now a days we use to deal with modules of Verilog or VHDL or combination of both. Mostly verification engineers are not allowed to modified these modules. But still SVA addition to these modules are required and easy to verify lot of RTL functionality. How can you add SVA to these modules?  Let’s find out !!

1. What is the difference between code coverage and functional coverage?

There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification process.

In below example we can understand how we can enable or disable a specific constraint whenever we need to do.