The term Asic stands for Application Specific Integrated Circuit. Is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. Generally an ASIC design will be undertaken for a product that will have a large production run,

Introduction

How can you visualize the relationship between classes and objects in SystemVerilog? This is the first post in a series on Object-Oriented Programming in SystemVerilog and UVM.

Introduction

What can you describe with Object-Oriented Programming? When I learned OOP, we had cute classes like animals, cars, and houses.

Friends, In this post I thought to present a quick reference for SystemVerilog (SV) Data Types which are the key elements in the foundation of any UVM based Verification Environment.

What is a Configuration Object in UVM & What is its utility..??

We heard about “Configuration Object“ and its usage/requirement in many places inside an UVM based Verification Environment.

Friends, since we already know that UVM is a fairly large Functional Verification Methdology & it involves many different concepts which I’m trying to cover one after another.

We know that UVM is a fairly complex Verification Environment since many things happens inside of the Environment on the fly and signal level details involved are limited to the Interface/Virtual Interface level. Component hierarchy is created, Virtual Interface and Configuration Objects are passed from the Test to the Driver,

Hi Friends, This time I decided to write about Assertions. I personally feels Assertions are very handy and highly useful asset when we talk about Functional Verification i.e. finding the bugs in the given RTL design & ensuring Verification completeness.

We discussed in the previous post i.e. “SystemVerilog Inheritance” about Up-Casting & Down-Casting. But the question is – Why do we want to downcast an Object which is hold by a Base Class variable? That’s where SystemVerilog Polymorphism comes into play.