PCMCIA Defines both the Electrical and Physical specifications for a 68 pin interface residing in one of 3 form factors, which differ only in thickness;

     Type I: 3.3mm x 85.6mm x 54.0mm (TxLxW), Version 2.1 allows the length to increase 50mm to 135mm
     Type II: 5.0mm x 85.6mm x 54.0mm (TxLxW), Version 2.1 allows the length to increase 50mm to 135mm
     Type III: 10.5mm x 85.6mm x 54.0mm (TxLxW)

   IDE / ATA Parallel Bus Description

      Nominally called the IDE (Integrated Drive Electronics) bus; how ever it's more correctly known as the ATA (Advanced Technology Attachment) specification [ATA Bus].

   Serial ATA Description

     The Serial ATA bus [SATA] is the serial version of the IDE [ATA] spec. SATA uses a 4 conductor cable with two differential pairs [Tx/Rx], plus an additional three grounds pins and a separate power connector. Data runs at 150MBps [1.5GHz] using 8B/10B encoding and 250mV signal swings, with a maximum bus length of 1 meter.

    Gigabit Ethernet Description

      The Ethernet standard uses Manchester Encoding and Decoding. Access control is gained via Carrier Sense, Multiple Access with Collision Detect (CSMA_CD). However 10 Gigabit Ethernet [10GE] only uses Full-duplex, so CSMA/CD is not required. Preamble Field:

   PCI Express Bus Description

     A description of the new Serial PCI Bus "PCI Express".
     The PCI Express [PCIe] bus defines the Electrical, topology and protocol for the physical layer of a point to point serial interface over copper wire or optical fiber.

      I²S Bus (IIS, or I2S) is a serial bus designed for digital audio devices. The I2S design handles audio data separately from clock signals. An I2S bus design consists of three serial bus lines: a line with two time-division multiplexing (TDM) data channels [SD], a word select line [WS], and a clock line [SCK].

     SCI [Serial Communications Interface] is an asynchronous serial communications bus used between uP [CPUs] and peripheral devices [EPROMs for example].

     Two signal lines are used with SCI: TXD [Transmit], and RXD [Receive].
The two wire SCI bus operates in Full-duplex mode [transmitting and receiving at the same time.

     IEEE Std 1149.1-1990 JTAG (Joint Test Action Group); Test Access Port and Boundary-Scan Architecture. This is a serial bus with four signals: Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO). The bus is used as a test bus for the 'Boundary-Scan' of ICs, as in Design-For-Testability (DFT). To use JTAG, during the design, you most select JTAG compatible devices. ICs supporting JTAG will have the four additional pins listed above.

   I2C Bus Description

      I2C bus was developed by Philips Semiconductors [NXP], originally designed to be a battery control interface.
     The I2C interface standard defines both the electrical layer and protocol layer.
The I2C bus uses a bi-directional Serial Clock Line [SCL] and Serial Data Lines [SDA]. Both the SCL and SDA lines are pulled high via an Rp resistor.

    
     Cách đây 8 năm, khi ra đời vào năm 1996, giao diện AGP (Ac celerated Graphics Port, cổng đồ họa tăng tốc), đã nổi đình nổi đám vì giải phóng được băng thông xử lý tín hiệu đồ họa vốn bó rị ở 133MB/s của bus PCI. Tốc độ AGP 1X có băng thông 266MB/s và AGP 8X (hay AGP 3.0 theo đặc tả của Intel) hiện nay đạt 2,1GB/s.

    Vi mạch khuyếch đại thuật toán 741 có hai đầu vào

       + "INVERTING ( - )":Đảo

       + "NON-INVERTING (+)": Thuận và đầu ra ở chân 6.

     HDLC [High-level Data Link Control] is a group of protocols for transmitting [synchronous] data [Packets] between [Point-to-Point] nodes. In HDLC, data is organized into a frame. HDLC protocol resides with Layer 2 of the OSI model, the data link layer.

     HDLC uses zero insertion/deletion process [bit stuffing] to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. The HDLC frame is synchronous and therefore relies on the physical layer to provide method of clocking and synchronizing the transmission and reception of frames.

Introduction

 Being new to Verilog you might want to try some examples and try designing something new. I have listed the tool flow that could be used to achieve this. I have personally tried this flow and found this to be working just fine for me.