Lexical Conventions
The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog HDL is a case-sensitive language. All keywords are in lowercase.
White Space
White space can contain the characters for blanks, tabs, newlines, and form feeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings.
| White space characters are : |
- Blank spaces
- Tabs
- Carriage returns
- New-line
- Form-feeds
| Examples of White Spaces |
| Functional Equivalent Code |
| Bad Code : Never write code like this. |
1 module addbit(a,b,ci,sum,co);
2 input a,b,ci;output sum co;
3 wire a,b,ci,sum,co;endmodule
Good Code : Nice way to write code.
|
| 1 module addbit ( 2 a, 3 b, 4 ci, 5 sum, 6 co); 7 input a; 8 input b; 9 input ci; 10 output sum; 11 output co; 12 wire a; 13 wire b; 14 wire ci; 15 wire sum; 16 wire co; 17 18 endmodule |
| Comments | |
| There are two forms to introduce comments. | |
| . | |
- Single line comments begin with the token // and end with a carriage return
- Multi line comments begin with the token /* and end with the token */
| Examples of Comments |
| 1 /* This is a 2 Multi line comment 3 example */ 4 module addbit ( 5 a, 6 b, 7 ci, 8 sum, 9 co); 10 11 // Input Ports Single line comment 12 input a; 13 input b; 14 input ci; 15 // Output ports 16 output sum; 17 output co; 18 // Data Types 19 wire a; 20 wire b; 21 wire ci; 22 wire sum; 23 wire co; 24 25 endmodule |
| Case Sensitivity |
| 1 input // a Verilog Keyword 2 wire // a Verilog Keyword 3 WIRE // a unique name ( not a keyword) 4 Wire // a unique name (not a keyword) |
| NOTE : Never use Verilog keywords as unique names, even if the case is different. |
| Identifiers |
| Identifiers are names used to give an object, such as a register or a function or a module, a name so that it can be referenced from other places in a description. |
- Identifiers must begin with an alphabetic character or the underscore character (a-z A-Z _ )
- Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
- Identifiers can be up to 1024 characters long
| Examples of legal identifiers |
| data_input mu |
| clk_input my$clk |
| i386 A |
| Escaped Identifiers |
| Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped identifiers provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal). |
- Escaped identifiers begin with the back slash ( \ )
- Entire identifier is escaped by the back slash.
- Escaped identifier is terminated by white space (Characters such as commas, parentheses, and semicolons become part of the escaped identifier unless preceded by a white space)
- Terminate escaped identifiers with white space, otherwise characters that should follow the identifier are considered as part of it.
| Examples of escape identifiers |
| Verilog does not allow to identifier to start with a numeric character. So if you really want to use a identifier to start with a numeric value then use a escape character as shown below. |
| 1 // There must be white space after the 2 // string which uses escape character 3 module \1dff ( 4 q, // Q output 5 \q~ , // Q_out output 6 d, // D input 7 cl$k, // CLOCK input 8 \reset* // Reset input 9 ); 10 11 input d, cl$k, \reset* ; 12 output q, \q~ ; 13 14 endmodule |
Bạn Có Đam Mê Với Vi Mạch hay Nhúng - Bạn Muốn Trau Dồi Thêm Kĩ Năng
Mong Muốn Có Thêm Cơ Hội Trong Công Việc
Và Trở Thành Một Người Có Giá Trị Hơn
Bạn Chưa Biết Phương Thức Nào Nhanh Chóng Để Đạt Được Chúng
Hãy Để Chúng Tôi Hỗ Trợ Cho Bạn. SEMICON
