Please refer to dual port RAM
Table 1. General Benefits / Drawbacks of Dual-Ports
| | Aynchronous | Synchronous |
| Benefits | More simple interface
Legacy design that is common | Higher bandwidth capabilities |
| Drawbacks | Lower bandwidth capabilities | More complicated interface |
Also, processors that are fast don't necessarily mean their external memory interfaces are fast. Some 400-MHz DSPs offer asynchronous SRAM interfaces only. In general, it is best to try to match the maximum speed and type of interfaces that the processors offer. For example, if both processors offer synchronous memory interfaces, one can run at a maximum of 70 MHz, one can run at a maximum of 133 MHz, then a synchronous dual-port that runs at least 133 MHz would be recommended.
1 //-----------------------------------------------------
2 // Design Name : ram_sp_ar_aw
3 // File Name : ram_sp_ar_aw.v
4 // Function : Asynchronous read write RAM
5 // Coder : -
6 //-----------------------------------------------------
7 module ram_sp_ar_aw (
8 address , // Address Input
9 data , // Data bi-directional
10 cs , // Chip Select
11 we , // Write Enable/Read Enable
12 oe // Output Enable
13 );
14 parameter DATA_WIDTH = 8 ;
15 parameter ADDR_WIDTH = 8 ;
16 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
17
18 //--------------Input Ports-----------------------
19 input [ADDR_WIDTH-1:0] address ;
20 input cs ;
21 input we ;
22 input oe ;
23
24 //--------------Inout Ports-----------------------
25 inout [DATA_WIDTH-1:0] data ;
26
27 //--------------Internal variables----------------
28 reg [DATA_WIDTH-1:0] data_out ;
29 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
30
31 //--------------Code Starts Here------------------
32
33 // Tri-State Buffer control
34 // output : When we = 0, oe = 1, cs = 1
35 assign data = (cs && oe && ! we) ? data_out : 8'bz;
36
37 // Memory Write Block
38 // Write Operation : When we = 1, cs = 1
39 always @ (address or data or cs or we)
40 begin : MEM_WRITE
41 if ( cs && we ) begin
42 mem[address] = data;
43 end
44 end
45
46 // Memory Read Block
47 // Read Operation : When we = 0, oe = 1, cs = 1
48 always @ (address or cs or we or oe)
49 begin : MEM_READ
50 if (cs && ! we && oe) begin
51 data_out = mem[address];
52 end
53 end
54
55 endmodule // End of Module ram_sp_ar_aw
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