
Introduction
We saw in last chapter basic introduction to Processes. There are three types of processes in SystemC. Processes are not hierarchical, so no process will call another process directly.
Processes can call methods and functions that are not processes. Processes have sensitivity lists, i.e. a list of signals that cause the process to be invoked, whenever the value of a signal in this list changes. Processes cause other processes to execute by assigning new values to signals in the sensitivity list of the other process.
Each of this processes will be discussed in detail in next few pages.
- Methods
- Edge Sensitive
- Level Sensitive
- Threads
- Clocked Threads
Methods
Methods behaves like a function, when called it gets started and executes and returns execution back to calling mechanism. A method is called when ever the event in the sensitivity list changes. Like always block in Verilog. Triggering event in sensitive list can be either edge sensitive or level sensitive.
Note : Sensitive list signals which trigger a process can be a signal or local variable or port.
The input signals that cause the process to reactivate are specified by the sensitivity list. The sensitivity list is specified in the module constructor
Example Methods
1 //-----------------------------------------------------
2 // This is my second Systemc Example
3 // Design Name : first_counter
4 // File Name : first_counter.cpp
5 // Function : This is a 4 bit up-counter with
6 // Synchronous active high reset and
7 // with active high enable signal
8 //-----------------------------------------------------
9 #include "systemc.h"
10
11 SC_MODULE (first_counter) {
12 sc_in_clk clock ; // Clock input of the design
13 sc_in<bool> reset ; // active high, synchronous Reset input
14 sc_in<bool> enable; // Active high enable signal for counter
15 sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter
16
17 //------------Local Variables Here---------------------
18 sc_uint<4> count;
19
20 //------------Code Starts Here-------------------------
21 // Below function implements actual counter logic
22 void incr_count () {
23 // At every rising edge of clock we check if reset is active
24 // If active, we load the counter output with 4'b0000
25 if (reset.read() == 1) {
26 count = 0;
27 counter_out.write(count);
28 // If enable is active, then we increment the counter
29 } else if (enable.read() == 1) {
30 count = count + 1;
31 counter_out.write(count);
32 }
33 } // End of function incr_count
34
35 // Below functions prints value of count when ever it changes
36 void print_count () {
37 cout<<"@" << sc_time_stamp() <<
38 " :: Counter Value "<endl;
39 }
40
41 // Constructor for the counter
42 // Since this counter is a positive edge trigged one,
43 // We trigger the below block with respect to positive
44 // edge of the clock and also when ever reset changes state
45 SC_CTOR(first_counter) {
46 // Edge and level sensitive
47 SC_METHOD(incr_count);
48 sensitive << reset;
49 sensitive << clock.pos();
50 // Level Sensitive method
51 SC_METHOD(print_count);
52 sensitive << counter_out;
53 } // End of Constructor
54
55 }; // End of Module counter
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