Uniquify Viet Nam One Member LLCLevel 7, Thien Son building, 5 Nguyen Gia Thieu street, ward 6, district 3, HCMC / Level 5, Indochina Riverside Tower building, 74 Bach Dang street, Hai Chau 1 ward, Hai Chau district, Da Nang city.
Work Location: Da Nang, Ho Chi Minh
What We Can Offer
13th month salary
Performance bonus
Personal accident and Health insurances package for you and your family
What You Will Do
* Junior PD Engineer:
We are seeking a sharp and highly motivated person whom our experienced ASIC design team can teach and train into an excellent ASIC design engineer. Candidate will work closely with our industry experienced physical design and/or logical design ASIC team developing multi-million gate state of the art System-on-Chip (SoC) designs. Candidate will gain understanding and practical knowledge in physical design of ASICs. The internship will focus on the following but not limited to synthesis, simulation and verification, static timing analysis, power analysis, as well as physical implementation (ex. floorplanning, place&route) and verification. This is a great opportunity for anyone who wants to start a career in the ASIC design industry.
What You Are Good At
1. Job requirement -Junior PD Engineer:
• Completion of undergraduate program in Electrical Engineering or Computer Engineering.
• Strong analytical and critical thinking skills.
• Good communication skills, positive attitude, and ability to work in a team environment.
• Exposure to a scripting languages such as TCL, Perl, and/or Make is a plus.
• Good understanding of Fundamentals of Synchronous logic design.
• Coursework in digital IC design a plus.
• Experience with Verilog coding and verification a plus.
• Project or industry experience in ASIC is a plus.
2. Job requirement - Senior PD Engineer
• Bachelors or Master’s degree in Engineering with 2+ years of ASIC physical design ( place and route ) experience.
• Proven APR hands-on tapeout ASIC experiences in 45nm and/or below technologies, fluent with Netlist-to-GDS flow using Sysopsys/Cadence tools.
• Experienced to be an APR block owner or top-level integration/floorplanning/ APR engineer.
• Must be able to work independently, to collaborate with different teams, and to be flexible to take dynamic and challenging assignments. Must have good communication skills, and can take tapeout pressure.
• Experienced in Tcl/Perl scripting to innovate APR methodology.
• Low power implementation
• Familiar with synthesis (RTL to Netlist).
3. Job requirement - PD Manager
• 5+ years experience in physical design with CAD tools including vendors such as Cadence and Synopsys,
• Experience in digital design flows including RTL synthesis, STA, PNR and Physical Verification. Experience with Cadence, Synopsys tools a plus.
• Preferred if you have managed a team of Physical Design Engineers
• Strong understanding of LINUX & windows operating systems.
• Programming experience with tcl, Perl, and Shell
• Strong written and verbal communication skills.
• Positive attitude, desire to learn and contribute in a fast paced global team
Who You Will Report To
for this position you will report to Headquarter Senior PD Manager/ PD Manager
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About Our Company
Uniquify Viet Nam One Member LLCLevel 7, Thien Son building, 5 Nguyen Gia Thieu street, ward 6, district 3, HCMC / Level 5, Indochina Riverside Tower building, 74 Bach Dang street, Hai Chau 1 ward, Hai Chau district, Da Nang city.
Contact person: HR Department
Company size: 25-99
Headquartered in Silicon Valley, Uniquify(www.uniquify.com) is a privately held ASIC design services and semiconductor IP solutions provider. The company has design centers in Santa Clara, California, Pune, India, Ho Chi Minh city and Da Nang city; and it maintains sales offices in Austin, Santa Clara, Seoul, Taipei and Tel Aviv. Uniquify provides leading edge SoC design and IP solutions. We offer a wide range of “ideas2silicon” services that span design specification, RTL, logic design/verification, physical implementation, and manufacturing operations. Perseus, our proprietary design management system allows us to deliver consistent design closure and reduced schedules on even the most complex SoC designs
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