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Async Reset or Sync Reset for ASIC ?

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Q ASYNC OR SYNC RESET? which one is use more in ASIC industry?

Async reset with sync release is probably the most common. Sync reset is used occasionally though. Async has the obvious advantage that your PoR works before the clock is working. You need a sync release to avoid potential metastability and make sure FSM start in a consistent state.

Resetting all FF's in a FPGA is not a waste of area at all. Most FPGA's come with a built in global asynchronous reset for free. It is called the CONFIG pin. You assert the pin and it puts all of the FF's into a known reset state before the clock starts. That is why you don't use FF's with an asynchronous reset in an FPGA because you don't need two complete asynchronous reset systems.

Q. Where Async reset is useful ? 

Asynchronous reset is used where logic should get reset without having any dependency on clock. In high speed design, where every clock cycle is critical, Logic has to use async reset. Latency critical design also can not afford one clock cycle delay. 

Below is the comparison between asynchronous and synchronous resets. 

Asynchronous Reset Synchronous Reset 

Flip flop area is more ..

Flip flop is less in area and less complex
A glitch on reset line can reset the whole design ,
extra care has to be taken.
Glitch may not effectice as reset is active
on clock edge only.

Datapath is clear , no additional logic required due
to reset.
Additional combinational logic required
which may affect high speed datapath.
Same reset goes to thousands of flop (may be milions),  Capacitive load will be high. Reset buffer tree may have to be pipelined
to keep all resets occurring within the same
clock cycle
No dependency on clock. Clock has to be present for reset. 
ASIC have expicitly reset for initialization.
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Lần cập nhật cuối ( Thứ ba, 05 Tháng 10 2021 13:35 )