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Handling multiclock domain in design ( RTL + SDC )

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In today world, it is most likely design having multiple clocks and there will be signals crossing between those clock domain.  The one way to design such logic is writing FSM in both clock domain and keep request/ack mechanism. Request must be synchronized in destination clock domain and acknowledge must also be sync in destination clock.

Below is the simple example of clock domain crossing , output from flop "FA" is going into "FB" which is clocked by C2. 





Below are few points I remembered while working on multi clock domain.


1. Keep your logic separate in respective clock domain.
2. Write logic in one file or one module for one clock domain.
3. Write a wrapper and connect signals coming from different clock domain through a sync cell.
4. This way design will be clean.
5. One can easily identified the signals going from one clock domain to other clock domain.
6. This will help in cdc clean up , all cdc violations can be catched in one file.
7. Most of the time we experience issue in cdc cleaning, one should always keep in mind that signals going in sync cell ,should be a output from flop,  there should not be any combinational gates before sync cell.

For synchronization, there are different technique used in industry, they are all standard one.

To sync a single bit , a synchronizer with 2/3 flop stages is used. But signal should be level type to avoid any dependency on frequency.

To synchronize a bus, normally Async FIFO is used. Depth of FIFO will depend on certain parameters like input datarate, output datarate, latency , packet size,etc.

For communication between 2 FSM which are working in different clock domain, request and handshake with 2/3 stage sync cell prefer to use.

There are signals which are pseudo-static , those signal will not required any synchronization those will be static for the duration in which they are getting used :)
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Lần cập nhật cuối ( Thứ ba, 05 Tháng 10 2021 13:32 )  

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