Now a days , multiple clocks in a system are common due to increasing frequency and complexity. A CDC check is a must check on the design before tapping out as any CDC violation may be fatal and could be a cause of chip failure.
In one of my blog I have explained the basic technique used in synchronization , here I will more focus on few design rules related to convergence , divergence and re-convergence.


Convergence here is, two signals coming from different path and getting used in one combination logic gate and output of gate is getting synchronized in destination clock domain , please see the below figure.


Here the issue could be , a glitch may propagated into receiving clock domain , which can sample and cause a functional issue.

CDC tool will detect this kind of issue and will give it in report. Designer should analyze it and fix it properly. As a standard rule for CDC, before synchronizing the signal , there should not be any combinational logic , signal going into sync cell should be output of a flop otherwise tool will issue warning for that , which will be described later.

-------------------------------------------------------------------

Divergence 

Some time a good design style lead to chip failure .. but we are safe as this is not related to divergence :)
Divergence is , when a control signal synchronized at different places and output of those synchronizers used in combinational logic. CDC tool will report as divergence issue , here the issue could be a glitch because of different path delay ,  This may lead to a functional error in a chip.

Please see below figure  -



Here data_en_sync and addr_en_sync may have different path delay.
Other example of divergence is , using meta stable signal. look into below figure.


This is most common mistake made by designers, they used to put sync flop but they might see this violation reported by tool.. the reason is , if signal coming from combinational logic ,tool think the second flop of sync cell is actually first flop of sync cell  , and then output of sync cell is used in other logic , tool may issue this warning.

It is always better to flop the signal first and then synchronized it in destination clock domain.
Re-convergence 

Re-convergence is , different signals coming through sync cell is getting used in some logic , a simple form of this is , synchronization of the individual bits of a bus  .. due to this there could be skew in data arrival and there could be a chance one sync cell capturing data a bit late which may cause 1 cycle delay. In this case, arriving data will no more valid and called as corrupted data.


Below is the figure - 

This is all about the convergence, divergence, re-convergence ..

 Bạn Có Đam Mê Với Vi Mạch hay Nhúng      -     Bạn Muốn Trau Dồi Thêm Kĩ Năng