Now a days in many verification scenarios it require to create a set of random instructions or addresses with each unique values or we can say that no repeating values, usually represented as elements in a dynamic array. 

Earlier versions of SystemVerilog required you to use either nested foreach loops to constraint all combinations of array elements so that they would not be equal to each other. Or else repeatedly randomize one element at a time, and then constraining the next element to not be in the list of already generated values.

The new unique constraint (new feature of 1800-2012) lets you use one statement to constraint a set of variables or array elements to have unique values. 

In the following example when randomized, this class generates a set of ten unique values from 0 to 15.

 class set_unique_val;

rand bit [3:0] data[10];

constraint uniq { unique {data};

}

endclass : set_unique_val

You can also add other non-random variables to the set of unique values which has the effect of excluding the values of those variables from the set of unique values. 

In the following example when randomized, this class generates a set of ten unique values excluding the values 0, 5 and 15.

 class set_unique_val;

 rand bit [3:0] data[10];

const bit [3:0] excludes[] = {0, 15};

 constraint uniq {

unique {data, excludes, 5};

}

endclass : set_unique_val

endclass : set_unique_val 

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