Function

A Verilog HDL function is the same as a task, with very little differences, like function cannot drive more than one output, can not contain delays.

• functions are defined in the module in which they are used. It is possible to define functions in separate files and use compile directive 'include to include the function in the file which instantiates the task.
• functions can not include timing delays, like posedge, negedge, # delay, which means that functions should be executed in "zero" time delay.
• functions can have any number of inputs but only one output.
• The variables declared within the function are local to that function. The order of declaration within the function defines how the variables passed to the function by the caller are used.
• functions can take, drive, and source global variables, when no local variables are used. When local variables are used, basically output is assigned only at the end of function execution.
• functions can be used for modeling combinational logic.
• functions can call other functions, but can not call tasks.

Syntax

• A function begins with keyword function and ends with keyword endfunction
• inputs are declared after the keyword function.

Example - Simple Function

  1 module simple_function();

  2

  3 function  myfunction;

  4 input a, b, c, d;

  5 begin

  6   myfunction = ((a+b) + (c-d));

  7 end

  8 endfunction

  9

 10 endmodule
Example - Calling a Function

  1 module  function_calling(a, b, c, d, e, f);

  2                    

  3 input a, b, c, d, e ;

  4 output f;

  5 wire f;

  6 `include "myfunction.v"

  7      

  8 assign f =  (myfunction (a,b,c,d)) ? e :0;

  9      

 10 endmodule

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