Uniquify
2030 Fortune Drive — Suite 200 - San Jose, CA 95131.
- Hạn Chót Nộp Hồ Sơ: 30-09-2013
- Cấp Bậc
- Nhân viên
Headquartered in Silicon Valley, Uniquify (www.uniquify.com) is a privately held ASIC design services and semiconductor IP solutions provider. The company has design centers in Santa Clara, California and Pune, India; and it maintains sales offices in Austin, Santa Clara, Seoul, Taipei and Tel Aviv. Uniquify provides leading edge SoC design and IP solutions. We offer a wide range of “ideas2silicon” services that span design specification, RTL, logic design/verification, physical implementation, and manufacturing operations. Perseus, our proprietary design management system allows us to deliver consistent design closure and reduced schedules on even the most complex SoC designs. We are now setting up Uniquify in Viet Nam and seeking for candidates working in Viet Nam.
Qui mô công ty: 25-99
- Nơi Làm Viêc
- Hồ Chí Minh
- Ngành Nghề
- Điện/Điện tử
Công nghệ cao
IT-Phần cứng/Mạng
- Ngôn Ngữ Trình Bày Hồ Sơ
- Tiếng Anh
Mô Tả Công Việc
- Working as part of a team and under closer supervision, tasks include but are not limited to synthesis of RTL netlist, developement, design and implementation of top/block level floor-plans; performance of clock-tree synthesis and high fan-out net synthesis; plan place and route architecture; conduct static timing analysis.
- Implement DRC, LVS and Antenna; determine the cause of any potential cause for gate array failure, ensuring parasitic extraction; and, perform design validation and provide formal verification.
Yêu Cầu Công Việc
• Experience in gate level timing simulation and DFT related experience is a plus.
• Thorough understanding of verilog constructs and syntax is a must.
• The last 2 to 3 years of experience should be focused on ASIC verification both at a functional block level and a system level.
• Extremely well versed in verilog.
• Working knowledge of C/C++
• Additional working knowledge of System verilog and/or System C is desirable.
• Well versed in scripting languages like Perl etc.
• Demonstrated ability to write verification code and debug functional and system level issues by coordinating with individual designers and system architects.
