How to pass parameter in verilog design from the top module ?

There are different method to do that , when a module is instantiate with different usage, probably width is one of the parameter which may not be same for all instantiation.

 For example, There is a FIFO design in which depth of the FIFO is parameterized mean FIFO depth can be set from top module. In below design , we see how to do that.

module fifo (
 parameter DEPTH = 10
)
(
input addr[ ] ,
input data [] ,
....
...
...
);

endmodule


Now we want to use this module in design A.

module A (  input  A ,
                   input B
);

// While instantiating the module, parameter can also be passed to fifo module.
fifo  #( .DEPTH(16) ) inst_fifo
(
.addr(),
.data(),
...
...
)

endmodule

in fifo #( .DEPTH(16)) inst_fifo , we can use parameter also.

fifo  #(.DEPTH(FIFO1_DEPTH)) inst_fifo ..

There are different ways to pass the parameter from top module.

Above parameter can be pass to module in this way also.

fifo  #(FIFO1_DEPTH) inst_fifo ..

In this case , if there are more than 1 parameter then order should be followed.

If a module has localparam , then it can not be override.

We can override the default values, either using defparam or by passing a new set of parameters during instantiation. We call this parameter overriding.

A parameter is defined by Verilog as a constant value declared within the module structure. The value can be used to define a set of attributes for the module which can characterize its behavior as well as its physical representation.

Defined inside a module.
Local scope.
Maybe overridden at instantiation time.