Company Description:
Ampere is designing the future of hyperscale cloud and edge computing with its 64-bit Arm server processor architecture. Born in and built for the cloud with a modern architecture, Ampere gives customers the freedom to accelerate the delivery of the most memory-intensive applications such as artificial intelligence, big data, machine learning and databases in the cloud. The Ampere eMAG family of products delivers the highest memory throughput and lowest TCO tailored for the emerging growth of cloud computing and next-generation data centers.
Our Story
Like the scientist behind its name, Ampere employees are innovators. We understand the needs of cloud computing and different software requirements. We are inventing what comes next and looking at everything from the structure of memory and how efficient the system is, to considerations on speed, cost of electricity and ability to cool. Power, size, weight and cost are driving the technology requirements and the innovation to come.
Our world class team of engineers, with depth and expertise in the cloud and semiconductor industries, is not only focused on the development of new semiconductor designs but also building out the first software ecosystem for Arm®-based server processors. Through the Ampere approach to the cloud and edge, we give our customers the freedom to challenge the status quo and accelerate next-generation data centers for the most memory-intensive applications. Given the challenge we have outlined, we are building a culture of entrepreneurs that ensure customers come first, proactively approaching industry challenges in the areas of security, power and performance, delivering results that matter most.
Job Description:
In this role, you will be responsible for ASIC physical design and implementation on our cutting edge ARMv8 based server on chip solutions (X-Gene) that will be the backbone of future data centers. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology nodes available in the industry.
Responsibilities:
- Responsible for all aspects of physical design from netlist to GDS on sub-micron node, 16nm or lower.
- Member of the team to develop physical design methodologies, flow customization/automation/optimization, floor-planning, power/clock distribution, IP block assembly, place & route, and timing closure.
- Own all the steps from (RTL/Netlist) to GDS for large functional blocks.
- Perform power and noise analysis, RC extraction, LEC, physical verification, and other sign-off checks.
- Implement design ECO to fix functional, timing, design constraints, crosstalk issues, etc. for pre- and post-layout.
Qualifications:
- Have one year experience in ASIC Physical Design.
- Have some basic working knowledge of Semiconductor devices, VLSI designs.
- Knowledge in ASIC design flow, EDA tools, timing analysis, is a plus.
- Familiar with UNIX, C, Verilog and Office applications.
- Familiar with scripting languages like TCL, Perl, Python.
- Good understanding on microprocessor, CPU-based architecture, interfaces like PCI, DDR.
- Good communication and teamwork skills.
- Good English communications skills, both verbal and writing.
Education:
- BS/MS in Electronics/Physics/Computer Science with GPA 7.0 above.
We are an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability status, protected veteran status, or any other characteristic protected by law.
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